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Wire segments may start, end, or pass through a switch block unbroken. Each short wire segment spans one logic block while long wire segments span multiple logic blocks . 1 FPGA Routing Architecture Overview 49 The organization of segment-to-segment connections inside a switch block has been a topic of significant study. Early switch block designers [208, 220] typically assumed a simple FPGA routing structure which only contained wire segments which span a single logic block throughout while still supporting Fs = 3.
8 Heterogeneity Up to this point, we have discussed the architectural trade-offs of a specific logic block choice or mixtures of different general purpose logic blocks. By contrast, any function that is implemented directly in specific-purpose logic on the FPGA will typically have superior area, speed, and power consumption over its implementation in generalpurpose logic blocks. However, if the function is not used in a target application, the silicon area devoted to the function will be wasted, causing a net reduction in area efficiency.
The work of [7, 8, 9] first explored the effect of lookup table (LUT) size on area and speed performance. 2 illustrates the basic trade-off discussed above, for area. 2 is the size of the lookup table (or K, the number of inputs to the lookup table). For this architecture, a “cluster” size of 1 was used, which means that each logic block contained exactly one LUT and flip–flop. 2 gives the geometric average of the number of K-input LUT/flip–flop blocks needed to implement the 28 circuits used in the experiment.