Download e-book for iPad: Design Automation for Timing-Driven Layout Synthesis by Sachin S. Sapatnekar, Sung-Mo Kang (auth.)

By Sachin S. Sapatnekar, Sung-Mo Kang (auth.)

Moore's legislation [Noy77], which estimated that the variety of units in­ tegrated on a chip will be doubled each years, was once actual for a couple of years. just recently has the extent of integration be­ gun to decelerate a little as a result actual limits of integration expertise. Advances in silicon expertise have allowed Ie layout­ ers to combine various million transistors on a chip; even an entire procedure of reasonable complexity can now be carried out on a unmarried chip. to maintain speed with the expanding complexity in very huge scale built-in (VLSI) circuits, the productiveness of chip designers must raise on the related cost because the point of integration. with no such a rise in productiveness, the layout of complicated structures is probably not achieveable inside an affordable timeframe. The speedily expanding complexity of VLSI circuits has made de- 1 2 advent signal automation an absolute necessity, because the required raise in productiveness can basically be comprehensive with using refined layout instruments. Such instruments additionally allow designers to accomplish trade-off analyses of other good judgment implementations and to make well-informed layout decisions.

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Tb = t~ - t2, the rise/fall delay. Given tl and the two delay quan- tities, ti and t~ can easily be computed. tb, collectively. to for standard primitives. in. The circuit is then simulated using an accurate circuit simulator, such as SPICE2 [N ag75], which calculates the falling output waveform, yo. tb, are found. , type 1, with the same slew rate as before, and two more delay values are computed. 40 DELAY ESTIMATION This experiment is then repeated with input ramps of different slew rates, producing a delay table with four delay values (namely, and ~t2' ~tl for type 0 and type 1) for each value of ~in.

Hence RC models, rather than 20 DELAY ESTIMATION RLC models, for interconnect are considered adequate. Strictly speaking, interconnect is a distributed system that is better represented by distributed resistors and capacitors, rather than by lumped elements. However, since lumped elements are easier to analyze, such models are favored over distributed models, especially for circuits where the operating frequency is not very high. 6(a). ;------------: ;-----------: ;-------------:-.................

10. At) = viet). 20) is conservative, the expression on the right-hand side is a good qualitative indicator of the distance between the bounds. It may be pointed out that the functions lli and Vi are one-to-one functions of t. Hence, bounds on the delay t(V), the time required by the step response to cross a voltage threshold V, can easily be obtained from the above expression. lli. - TRI,. 22) A more detailed discussion on the tightness of these bounds can be found in [Wya87]. 3. 3 31 Macromodeling Macromodeling [Mat85, Che88] is a technique that was developed to help analyze large circuits.

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